1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to an electrostatic discharge protection circuit in a semiconductor device.
2. Description of Related Art
A semiconductor device is provided with an electrostatic discharge protection circuit in order to protect an internal circuit against ESD (electrostatic discharge) surge which is applied to an input/output pad. One well-known circuit topology of the electrostatic discharge protection circuit is that uses an active element such as a thyristor and a bipolar transistor. The electrostatic discharge protection circuit using the active element has an advantage in that discharge capacity is high because it performs an active operation when surge is inputted, and thus the circuit is widely used (see for example: “A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads”, IEEE Electron Device Letters, vol. 12, No. 1, January 1991 (non-patent document 1) and “GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Sub-Micron CMOS Processes”, EOS/ESD Symposium 2001, p. 22 (non-patent document 2)).
It is desired for the electrostatic discharge protection circuit using the active element that a leakage current at a time of a normal operation is small and a trigger voltage when the ESD surge is applied is low. A configuration of the electrostatic discharge protection circuit to satisfy such requirements is disclosed in “A Low-Leakage SCR Design Using Trigger-PMOS Modulations for ESD Protection”, EOS/ESD Symposium 07-376 (non-patent document 3) and Japanese Patent Publication JP-2008-218886A.
FIG. 1 is a circuit diagram showing the configuration of the electrostatic discharge protection circuit disclosed in the non-patent document 3 (note that an electrostatic discharge protection circuit having the same configuration is disclosed also in Japanese Patent Publication JP-2008-218886A). The electrostatic discharge protection circuit shown in FIG. 1 has a VDD pad 101, a signal pad 102, a VSS pad 103, a power supply line 104, a signal line 105, a ground line 106, a thyristor 107, an ESD protection diode D1 and a PMOS transistor P1.
In the electrostatic discharge protection circuit shown in FIG. 1, the PMOS transistor P1 functions as a trigger element for supplying a trigger current to the thyristor 107. The electrostatic discharge protection circuit shown in FIG. 1 can treat various modes of ESD surges applied to the VDD pad 101, the signal pad 102 and the VSS pad 103. However, the description hereinafter is made only for an operation in a case where an ESD surge such that a potential of the signal pad 102 is positive as compared with a potential of the VSS pad 103 is applied between the signal pad 102 and the VSS pad 103, which is a subject of the present invention.
In the case where the ESD surge such that the potential of the signal pad 102 is positive as compared with the potential of the VSS pad 103 is applied between the signal pad 102 and the VSS pad 103, the power supply line 104 becomes a floating state. Since a power supply capacitor Cx is parasitically or intentionally provided between the power supply line 104 and the ground line 106, the power supply line 104 is fixed at substantially the same potential as that of the ground line 106 until the power supply capacitor Cx is charged. When the positive ESD surge is applied to the signal pad 102 and a potential of the signal line 105 at the same potential is increased, a source potential of the PMOS transistor P1 becomes higher than a gate potential thereof (being the same potential as that of the power supply line 104 and substantially the same potential as that of the ground line 106) and a gate-source voltage of the PMOS transistor P1 exceeds a threshold voltage. When the gate-source voltage of the PMOS transistor P1 exceeds the threshold voltage, the PMOS transistor P1 operates to supply the trigger current to the thyristor 107, and thereby the thyristor 107 operates to discharge the ESD surge.
The inventor of the present application has recognized the following points. One problem in the configuration of the electrostatic discharge protection circuit shown in FIG. 1 is that the PMOS transistor P1 may become hard to perform a low-voltage operation, depending on a configuration of the internal circuit to be protected and other associated circuits/associated elements. For example, let us consider a case shown in FIG. 2A where an output circuit is used as an internal circuit connected to the signal line 105 and a PMOS transistor P11 is used as a pull-up transistor of the output circuit. In this case, when the ESD surge such that the potential of the signal pad 102 is positive is applied, a parasitic diode D11 formed between the signal line 105 and the power supply line 104 by a P-type diffusion layer of a drain and an N-well of a backgate of the PMOS transistor P11 is forward biased (see FIG. 2B). Accordingly, a charging path passing through the parasitic diode D11 is formed and thus the power supply line 104 is charged rapidly. When the power supply line 104 is charged, the potential of the power supply line 104 increases following the potential of the signal line 105 and thus the gate-source voltage of the PMOS transistor P1 hardly increases. As a result, in the circuit configuration shown in FIG. 2A, a voltage between the signal line 105 and the power supply line 104 becomes as small as a voltage of the forward bias voltage Vf_D11 of the parasitic diode D11, namely about 0.6 V to 1.1 V.
However, in order for the PMOS transistor P1 to operate, the source-gate voltage Vgs of the PMOS transistor P1 needs to exceed the threshold voltage Vt_P1. By using a base-emitter voltage Vbe of a PNP transistor Q1 in the thyristor 107, the source-gate voltage Vgs of the PMOS transistor P1 can be expressed by the following equation (1).Vgs=Vf—D11−Vbe  Equation (1):
Therefore, in order to operate the PMOS transistor P1, a condition expressed by the following equation (2) needs to be satisfied.Vf—D11−Vbe>Vt—P1  Equation (2):
Here, “Vf_D11” and “Vbe” each is a forward bias voltage of a PN junction, which is approximately 0.6 V. That is, the condition expressed by the equation (2) is not satisfied depending on an operation condition, which results in a problem that the thyristor 107 fails to perform the discharging operation. Even if a large current flows through the parasitic diode D11 and the condition expressed by the equation (2) is satisfied, a difference between the source-gate voltage Vgs of the PMOS transistor P1 and its threshold voltage Vt_P1 becomes small, and thus a current flowing through the PMOS transistor P1, namely the trigger current may become small. If the trigger current supplied to the thyristor 107 becomes small, the thyristor 107 may be broken without operating or the internal circuit may be broken due to application of voltage stress.
The same applies to a case shown in FIG. 3 where an electrostatic discharge protection diode D12 is provided between the signal line 105 and the power supply line 104. Also in this case, when the ESD surge such that the potential of the signal pad 102 is positive is applied, the electrostatic discharge protection diode D12 is forward biased. Accordingly, a charging path passing through the electrostatic discharge protection diode D12 is formed and thus the power supply line 104 is charged rapidly. When the power supply line 104 is charged, the potential of the power supply line 104 increases following the potential of the signal line 105 and thus the gate-source voltage of the PMOS transistor P1 hardly increases. This is not preferable because the PMOS transistor P1 may not operate or the trigger current may be reduced.